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| (R) STB70NF3LL N-CHANNEL 30V - 0.008 - 70A D2PAK LOW GATE CHARGE STripFETTM POWER MOSFET PRELIMINARY DATA T YPE STB70NF3LL s s s s V DSS 30 V R DS(on) < 0.01 ID 70 A TYPICAL RDS(on) = 0.01 @ 4.5V OPTIMAL RDS(on) x Qg TRADE-OFF @ 4.5V CONDUCTION LOSSES REDUCED SWITCHING LOSSES REDUCED 3 1 DESCRIPTION This application specific Power Mosfet is the third generation of STMicroelectronics unique "Single Feature SizeTM" strip-based process. The resulting transistor shows the best trade-off between on-resistance and gate charge. When used as high and low side in buck regulators, it gives the best performance in terms of both conduction and switching losses. This is extremely important for motherboards where fast switching and high efficiency are of paramount importance. APPLICATIONS s SPECIFICALLY DESIGNED AND OPTIMISED FOR HIGH EFFICIENCY CPU CORE DC/DC CONVERTERS D2PAK TO-263 ADD SUFFIX "T4" FOR ORDERING IN TAPE & REEL INTERNAL SCHEMATIC DIAGRAM ABSOLUTE MAXIMUM RATINGS Symbol V DS V DGR V GS ID ID I DM (*) P tot Ts tg Tj Parameter Drain-source Voltage (VGS = 0) Drain- gate Voltage (R GS = 20 k) G ate-source Voltage Drain Current (continuous) at Tc = 25 C Drain Current (continuous) at Tc = 100 C Drain Current (pulsed) T otal Dissipation at Tc = 25 C Derating Factor Storage Temperature Max. Operating Junction Temperature o o o Value 30 30 15 70 50 280 100 0.67 -65 to 175 175 Un it V V V A A A W W /o C o o C C (*) Pulse width limited by safe operating area May 2000 1/6 STB70NF3LL THERMAL DATA R thj -case R thj -amb Tl Thermal Resistance Junction-case Max Thermal Resistance Junction-ambient Max Maximum Lead Temperature F or Soldering Purpose 1.5 62.5 300 o o C/W C/W o C ELECTRICAL CHARACTERISTICS (Tcase = 25 oC unless otherwise specified) OFF Symbo l V (BR)DSS I DSS IGSS Parameter Drain-source Breakdown Voltage Test Con ditions I D = 250 A V GS = 0 Min. 30 1 10 100 Typ. Max. Unit V A A nA V DS = Max Rating Zero Gate Voltage Drain Current (V GS = 0) V DS = Max Rating Gate-body Leakage Current (VDS = 0) V GS = 20 V T c =125 oC ON () Symbo l V GS(th) R DS(on) I D(o n) Parameter Gate Threshold Voltage V DS = V GS Static Drain-source On Resistance On State Drain Current V GS = 10V V GS = 4.5V Test Con ditions ID = 250 A I D = 35 A I D = 18 A 70 Min. 1 0.008 0.01 0.01 0.012 Typ. Max. Unit V A V DS > ID(o n) x R DS(on )ma x V GS = 10 V DYNAMIC Symbo l g f s () C iss C os s C rss Parameter Forward Transconductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Test Con ditions V DS > ID(o n) x R DS(on )ma x V DS = 25 V f = 1 MHz I D =35 A V GS = 0 Min. Typ. 40 1700 500 115 Max. Unit S pF pF pF 2/6 STB70NF3LL ELECTRICAL CHARACTERISTICS (continued) SWITCHING ON Symbo l t d(on) tr Qg Q gs Q gd Parameter Turn-on Delay T ime Rise Time Total G ate Charge Gate-Source Charge Gate-Drain Charge Test Con ditions V DD = 15 V I D = 35 A R G = 4.7 V GS = 4.5 V (Resistive Load, see fig. 3) V DD = 24 V ID = 70 A V GS = 10 V Min. Typ. 20 350 43 10 10 56 Max. Unit ns ns nC nC nC SWITCHING OFF Symbo l t d(of f) tf Parameter Turn-off Delay T ime Fall T ime Test Con ditions V DD = 15 V I D = 35 A V GS = 4.5 V R G = 4.7 (Resistive Load, see fig. 3) Min. Typ. 35 65 Max. Unit ns ns SOURCE DRAIN DIODE Symbo l ISD I SDM (*) V SD () t rr Q rr I RRM Parameter Source-drain Current Source-drain Current (pulsed) Forward On Voltage Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current I SD =70 A V GS = 0 40 52 2.4 I SD = 70 A di/dt = 100 A/s o T j = 150 C V DD = 15 V (see test circuit, fig. 5) Test Con ditions Min. Typ. Max. 70 280 1.5 Unit A A V ns nC A () Pulsed: Pulse duration = 300 s, duty cycle 1.5 % (*) Pulse width limited by safe operating area 3/6 STB70NF3LL Fig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform Fig. 3: Switching Times Test Circuits For Resistive Load Fig. 4: Gate Charge test Circuit Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times 4/6 STB70NF3LL TO-263 (D2PAK) MECHANICAL DATA mm MIN. A A1 B B2 C C2 D E G L L2 L3 4.4 2.49 0.7 1.14 0.45 1.21 8.95 10 4.88 15 1.27 1.4 TYP. MAX. 4.6 2.69 0.93 1.7 0.6 1.36 9.35 10.4 5.28 15.85 1.4 1.75 MIN. 0.173 0.098 0.027 0.044 0.017 0.047 0.352 0.393 0.192 0.590 0.050 0.055 inch TYP. MAX. 0.181 0.106 0.036 0.067 0.023 0.053 0.368 0.409 0.208 0.624 0.055 0.068 DIM. D A C A2 DETAIL "A" A1 B2 B G C2 DETAIL"A" E L2 L L3 P011P6/E 5/6 STB70NF3LL Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a trademark of STMicroelectronics (c) 2000 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com 6/6 |
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